The storage capacity of semiconductor memory devices has continued to increase at a remarkable rate. The increase in storage capacity can be attributable to a number of factors, including but not limited to, advancements in processing technology and/or reductions in the size of various features within a semiconductor memory device. Reduced features sizes include smaller spacings between repeated structures (smaller "pitch"), as well as reductions in the size of particular components, such as conductive line widths, transistors, capacitors, and the like.
Due to the great number of memory cells and high complexity of most semiconductor memory devices, it can be very difficult to consistently manufacture devices that are completely free of defects. If all semiconductor devices having any sort of defect were completely discarded, the manufacturing yield of such devices would be significantly lowered. In order to increase fabrication yield, most semiconductor devices include some sort of redundancy scheme.
A redundancy circuit typically replaces one circuit element (such as a defective "ordinary" memory cell) with another (such as a redundant memory cell). In operation, when an address is applied to a memory device that corresponds to a defective ordinary memory cell, a redundancy circuit can detect such an address and prevent the defective ordinary memory cell from being accessed. Instead, the redundancy circuit can provide access to a redundant memory cell. In order to maintain operating speeds, it is desirable for an access to a redundant memory cell to be indistinguishable from an access to an ordinary memory cell and vice versa.
In this way, even if a semiconductor memory device includes defective memory cells (due to uncontrollable process variation, for example) it can still be fully functional through the use of redundancy circuits. This can allow semiconductor memory devices with defective memory cells to be packaged and provided as working devices. Consequently, the overall fabrication yield can be increased.
In many cases, even in the most advanced manufacturing processes, increases in semiconductor memory capacity may result in corresponding increases in defects. Thus, as semiconductor memory devices continue to increase in capacity, more and more redundant memory cells are included to account for possible defects. The resulting increases in redundancy circuits arising from larger numbers of memory cells may adversely affect access times to the semiconductor memory device.
To better understand the various features and advantages of the present invention, a conventional semiconductor memory device with redundancy circuits will now be described. A conventional semiconductor memory device is shown in FIG. 21, and may be a synchronous semiconductor memory. As shown in FIG. 21, a semiconductor device may include ordinary memory cell areas 001, a redundant memory cell area 002, Y decoder circuits 003, a redundancy Y switching circuit 004, Y predecoder circuits 005, and a redundancy circuit section 006.
Y decoder circuits 003 and redundancy switching circuit 004 may be situated in close proximity to cell areas 001 and 002. Y predecoder circuits 005 and redundancy circuit section 006 may be situated in the periphery of cell areas (001 and 002), but likewise are in close proximity to such areas.
Y decoder and Y predecoder circuits (003 and 005) can be provided to access ordinary memory cells in ordinary memory cell areas 001. As but one example, Y predecoder circuits 005 may receive address signals, and generate predecoded address signals. Such predecoded address signals may be received by Y decoder circuits 003 that may then select one or more ordinary memory cells.
Redundancy circuit section 006 and redundancy Y switching circuit 004 can be provided to access redundant memory cells in redundant memory cell area 002. More particularly, redundancy circuit section and redundancy switching circuit (006 and 004) may receive address values and determine if an address value corresponds to a defective ordinary memory cell. If an address value does not correspond to a defective memory cell, an access can proceed as described above with respect to Y decoder and Y predecoder circuits (003 and 005). If an address corresponds to a defective ordinary memory cell, redundancy circuit section and redundancy switching circuit (006 and 004) can disable a Y predecoder circuit 005 and select one or more redundant memory cells from a redundant memory cell area 002.
Referring now to FIG. 22, a diagram is set forth showing various signals that may be applied and generated in the conventional memory device of FIG. 21. To that extent, like structures will be referred to by the same reference characters.
As shown in FIG. 22, an address signal YAjT may be received. In the particular example illustrated, within the term "YAjT" a value j may be a positive integer and the value T may indicate a logic high level.
Various signals are generated depending upon to whether or not the address signal YAjT corresponds to a defective ordinary memory cell.
If an address signal YAjT does not correspond to a defective ordinary memory cell, a redundancy circuit section 006 can receive the address and determine that it does not correspond to a defective memory cell. Consequently, decode enable signal YREDB can remain active and redundancy Y switching activation signals RYS can remain inactive. With decode enable signals YREDB active, Y predecoder circuits 005 can predecode address signal YAjT and provide predecoded address signal YPRD to Y decoder circuits 003. According to predecoded address signals YPRD, Y decoder circuits 003 can access one or more ordinary memory cells (e.g., for a read or write operation) with Y select signals YSW. With redundancy switching activation signals RYS inactive, redundant memory cells in a redundant memory cell area 002 are not accessed.
If an address signal YAjT corresponds to a defective ordinary memory cell, a redundancy circuit section 006 can receive the address and determine such a correspondence. Consequently, decode enable signals YREDB can be deactivated and redundancy Y switching activation signals RYS can be activated. With decode enable signal YREDB inactive, Y predecoder circuits 005 can be disabled, and so do not generate predecoded address signal YPRD for Y decoder circuits 003. Thus, an ordinary memory cell is not accessed in response to an address signal YAjT. Instead, with redundancy Y switching activation signals RYS active, a redundancy switch circuit 004 can access one or more redundant memory cells according to redundancy Y select signals RYSW. In this way, a defective ordinary memory cell may be replaced by a redundant memory cell.
The operation of a redundancy circuit section 006 may be timed according to a clock synchronization signal YRD. A clock synchronization signal YRD may be a synchronous with an externally applied clock signal.
Various signals described with reference to FIG. 22 will now be described in more detail in FIG. 23. FIG. 23 is a representation of an integrated circuit "chip" that may include a conventional semiconductor memory device. As noted above, such a semiconductor memory device may be a synchronous device. In such a case, the synchronous semiconductor memory device may receive an external clock signal. Further, input signals may be received and output signals may be provided in synchronism with such an external clock signal.
In response to an external clock signal, a synchronous semiconductor memory device may generate an internal clock signal, shown as ICLK. An internal clock signal ICLK may be used to generate an address signal YAjT and a clock synchronization signal YRD. More particularly, a synchronous semiconductor memory device may include a clock synchronization signal generator 007 and a Y address signal generator 008. A Y address signal generator 008 can latch an externally applied address in synchronism with internal clock ICLK and provide an address signal YAjT. In addition, a clock synchronization signal generator 007 can generate a clock synchronization signal YRD in synchronism with an internal clock ICLK.
Having described the structure and operation of a conventional semiconductor memory device, an example of a conventional redundancy circuit section will now be described with reference to FIG. 24. The redundancy circuit section of FIG. 24 may be used in the previously described conventional semiconductor memory devices, and so is designated by the same reference character 006.
Referring now to FIG. 24, a redundancy circuit section 006 may include a number of redundancy circuits 009. Each redundancy circuit 009 may include a fuse node (FUSE 00-11). A fuse node (FUSE NODE 00-11) may be precharged to a high level, and then discharged if a received address value matches a defective address value programmed within the redundancy circuit 009. The redundancy circuit 009 for FUSE NODE 00 is shown in detail. The other redundancy circuits 009 (i.e., for FUSE NODES 01 to 11) may have the same configuration.
A redundancy circuit 009 may include a precharge device 020, an enable device 021, fuses 022 and corresponding detect transistors 023. In addition for each fuse 022 and detect transistor 023, there may be a complementary fuse 024 and complementary detect transistor 025. A precharge device 020 may be a p-channel transistor having a source-drain path between FUSE NODE 00 and a first power supply and a gate that receives a clock synchronization signal YRD. An enable device 021 may be an n-channel transistor having a source-drain path between FUSE NODE 00 and a second power supply (e.g., ground) and a gate that receives an enable signal .o slashed.. A fuse 022 may be arranged in series with the source-drain path of a detect transistor 023 between FUSE NODE 00 and the second power supply. A fuse 022 may be programmed (e.g., opened or kept intact) to store part of a defective address and a detect transistor 023 may be an n-channel transistor. In a similar fashion, a complementary fuse 024 may be arranged in series with the source-drain path of a complementary detect transistor 025 between FUSE NODE 00 and the second power supply. A complementary fuse 024 may also be programmed to store part of a defective address and a complementary detect transistor 025 may be an n-channel transistor.
As noted above, a redundancy circuit 009 may receive an address signal. Such an address signal is shown in FIG. 24 as address values YA0T to YA8T. As shown in the figure, address values (YA0T to YA8T) may be applied to the gates of detect transistors 023. Further, address values (YA0T to YA8T) may be inverted by inverters 026 and then provided to the gates of complementary detect transistors 025.
A redundancy circuit 009 may also include a latching circuit. A latching circuit can latch NODE 00 at a precharged value, and in addition, provide a redundancy Y activating signal RYS0. Such a latching circuit may include series connected inverters 027 and 028, as well as feedback transistor 029. The output of inverter 027 can provide a signal RYB.
Having described the various circuit components of a redundancy circuit 009, the operation of the redundancy circuit 009 will now be described. Prior to an access, a clock synchronization signal YRD may be low, while an enable signal .o slashed. may be also be low. Precharge device 020 can be turned on while enable device 021 can be turned off, and FUSE NODE 00 can be precharged to a first power supply level. With FUSE NODE 00 high, inverter 027 can turn on feedback transistor 029 thereby latching FUSE NODE 00 at the high level.
Next, clock synchronization signal YRD can transition high, and address values (YA0T to YA8T) can be applied to the redundancy circuit 009. Feedback transistor 029 can maintain FUSE NODE 00 at the precharged high level. The response of the redundancy circuit 009 can vary according to whether applied address values (YA0T to YA8T) match a defective address stored by fuses 022 and complementary fuses 023.
If the applied address values (YA0T to YA8T) do not match a defective address, FUSE NODE 00 can be discharged by at least one detect transistor 023 or complementary detect transistor 025 being turned on and overpowering feedback transistor 029. The discharging of FUSE NODE 00 can also result in the deactivation of redundancy Y activating signal RYS0.
If the applied address values (YA0T to YA8T) match a defective address, the particular state of fuses 022 and complementary fuses 024 can prevent FUSE NODE 00 from discharging, and FUSE NODE 00 can remain latched at the precharged high level. Further, redundancy Y activating signal RYS0 can remain activated.
A redundancy circuit section 006 may further include combining logic that can detect if a programmed defective address is detected by any of the redundancy circuits 009. If a defective address is not detected (i.e., an applied address corresponds to an ordinary memory cell) a decode enable signal YREDB can remain active. If, however, a defective address is not detected (i.e., an applied address corresponds to a defective ordinary memory cell) decode enable signal YREDB can be deactivated.
The combining logic of FIG. 24 includes NOR gates 030 and 031. Each NOR gate (030 and 031) may logically combine the state of two fuse nodes. Thus, if either FUSE NODE 00 or 01 is high, the output of NOR gate 030 YREB0 will be driven low. Similarly, if either FUSE NODE 10 or 11 is high, the output of NOR gate 031 YREB1 will be driven low. The outputs of NOR gates (030 and 031) may be logically combined in a NAND gate 032. Further, the output of NAND gate 032 YRE0 and the outputs (YER1 YER2) other such NAND gates (not shown) may be logically combined in a NOR gate 033. The output of NOR gate 033 may be a decode enable signal YREDB.
In the conventional example of FIG. 24, access to memory cells (both redundant and ordinary) can depend upon the level of decode enable signal YREDB. Thus, when access switches from an ordinary memory cell to a redundant memory cell, YREDB can transition from high to low and redundant Y select signals (RYSW) can be activated. Similarly, when access switches from a redundant memory cell to an ordinary memory cell, YREDB can transition from low to high and Y select signals RYSW can be activated.
As noted above, because semiconductor memory device capacity has been increasing. such devices have a larger number of redundant memory cells. Consequently, semiconductor memory devices can have larger areas, more logic stages and larger fuse nodes. Further, wiring loads, in particular the wiring load for decode enable signals YREDB call also be larger. For these and other reasons, the delay involved in switching between ordinary and redundant memory cell accesses can be considerable.
Such delays can adversely affect the operation of a semiconductor memory device: Access times can increase, or, in a worst case situation, erroneous data may result.
In light of the above drawbacks to conventional semiconductor memory devices, it would be desirable to arrive at some way of reducing delays associated with switching between a redundant memory cell access and ordinary memory cell access.